1. Field of the Invention
The invention relates to single-ended to differential converters, and more particularly to wide-band single-ended to differential converters (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology.
2. Description of the Related Art
FIG. 1 shows the prior art of a single to differential circuit which is directly derived from its bipolar counterpart, while FIG. 3 is the small signal version of FIG. 1. However, it is observed (and will be shown later) that the performance of this circuit cannot meet the requirement for a wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology, especially at high frequencies. FIG. 1 is a differential amplifier comprised of transistors M1 and M2, their sources are coupled to a reference potential via a tail current source transistor M3. Their drains are coupled each to a voltage supply VDD via resistive means RL1. The gate of M1 is connected to input INP via capacitive means CI1. Input VBIAS1 provides bias to the gates of M1 and M2 via resistive means RB1 and RB2, respectively. The gate of M2 is also connected to a reference potential via capacitive means CI2. VBIAS2 provides bias to the gate of M3. Outputs OUTA and OUTB are coupled to the drains of M1 and M2, respectively. FIG. 3, which shows parasitic gate-source capacitances CA and parasitic tail current capacitance CB will be discussed in detail in the Description of the Preferred Embodiment, because it directly bears on the design of the present invention.
Another prior art of a differential amplifier with capacitors for cancellation of the negative feedback action of the gate to drain parasitic capacitance CGD at high frequencies is explained in Alan B. Grebene, xe2x80x9cBipolar and MOS Analog Integrated Circuit Designxe2x80x9d, John Wiley and Sons, 1991, pp 415-416. This second prior art, however, does nothing to improve the amplitude and phase imbalances that we are concerned with.
The following US Patents relate to single-ended to differential converters:
1. U.S. Pat. No. 4,292,597 (Nimura et al.) Circuit for Converting Single-Ended Input Signals to a Pair of Differential Output Signals.
2. U.S. Pat. No. 4,369,411 (Nimura et al.) Circuit for Converting Single-Ended Input Signals to a Pair of Differential Output Signals.
3. U.S. Pat. No. 5,068,621 (Hayward et al.) Compensation Method and Apparatus for Enhancing Single Ended to Differential Conversion.
4. U.S. Pat. No. 5,220,286 (Nadeem) Single Ended to Fully Differential Converters, describes single-ended to differential converters using switched capacitor circuits. It is well known that the highest frequencies that can be handled by such circuits are in the range of a few hundreds of Kilohertz only.
5. U.S. Pat. No. 5,614,864 (Stubbe et al.) Single-Ended to Differential Converter with Relaxed Common-Mode Input Requirements.
6. U.S. Pat. No. 5,805,019 (Shin) Voltage Gain Amplifier for Converting a Single Input to a Differential Output, discloses single-ended to differential converters using switched capacitor circuits. It is well known that the highest frequencies that can be handled by such circuits are in the range of a few hundreds of Kilohertz only.
7. U.S. Pat. No. 5,896,053 (Prentice) Single Ended to Differential Converter and 50% Duty Cycle Signal Generator and Method, describes a circuit that can operate up to 300 MHz. But the implementation is with bipolar devices and is quite different from the invention described.
8. EP 0766381 (Stubbe et al.) Improved Single-Ended to Differential Converter with Relaxed Common-Mode Input Requirements, similar to U.S. Pat. No. 5,614,864 (Stubbe et al.) above.
9. EP 0472340 (Hayward et al.) A Compensation Method and Apparatus for Enhancing Single Ended to Differential Conversion, similar to U.S. Pat. No. 5,068,621 (Hayward et al.) above.
It is an object of the present invention to provide circuits and a method for a wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively, using CMOS technology.
These and many other objects have been achieved by the use of capacitive means CD across the gate and source of first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage. Using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well.